Patent US 8,729,933

A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%.