PROCESSING A FAST SPEED GRADE CIRCUIT DESIGN FOR USE ON A SLOWER SPEED GRADE INTEGRATED CIRCUIT

Up-binning a circuit design includes receiving a first bitstream specifying the circuit design. The circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit. Using a processor, a first parameter of the first bitstream is determined. The first parameter is applied to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design. A timing analysis is performed upon the parameterized hardware netlist. The process further includes determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit. The second speed grade is slower than the first speed grade.