System And Method For Automatic Timing-Based Register Placement and Register Location Adjustment In An Integrated Circuit (IC)

Patent №

US 8,762,909

Granted

2014-06-24

Filed 2013

Owner

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13796078

An embodiment of a method for register placement in an integrated circuit (IC) includes determining a data path between circuit elements, placing at least one register along the data path, performing a static timing analysis on the data path, extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments; processing the top-level timing data to determine whether the extended timing path violates a timing requirement, and moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated.

PlanningG06F 30/3315G06F 30/3312G06F 30/392G06F 2119/12

AI classification

Planning0.98
AI hardware0.02
Knowledge representation0.01
Vision0.01
Evolutionary computation0.00
Natural language0.00
Machine learning0.00
Speech0.00

Ownership

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

assignment · 299730706

Assignors

KOENIG, BRADY A., DIXON, STEPHEN L., GENTRY, JASON TODD

On an employer assignment, the assignors are typically the inventors.

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