RECONFIGURABLE ELEMENTS

The present invention provides for a multiprocessor device on either a chip or a stack of chips. The multiprocessor device includes a plurality of processing entities and a memory system. The multiprocessor device further includes at least one interface unit to at least one of an external memory and one or more peripherals. The multiprocessor device includes a bus system interconnecting the processing entities, the memory system and the at least one interface unit. Wherein, the memory system includes a plurality of cache segments, and the plurality of segments are located on a plurality of memory cores, each having a connection to the bus system.