MASTER-SLAVE FLIP-FLOP WITH REDUCED SETUP TIME

A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520) coupled to the output terminal of the transmission gate, and a two-input logic gate (525) having a first input terminal (541) coupled to the storage element, a parallel input terminal (542) coupled to the input terminal of the master stage, and an output terminal (543) that provides an output terminal of the master stage. A slave stage (503) has terminals for receiving second clock signals, wherein first clock signals are delayed relative to second clock signals.