Digital Period Divider

A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.