Patent US 8,909,745

Patent №

US 8,909,745

Granted

—

Owner

—

Lab

—

AI components

planning · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

13459135

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Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Planning AI hardwareG06F 15/7871G06F 8/654G06F 15/7892G06F 9/4418

Google Patents

AI classification

AI hardware0.98

Planning0.57

Natural language0.02

Knowledge representation0.00

Speech0.00

Machine learning0.00

Vision0.00

Evolutionary computation0.00

Cites (11)

METHOD AND SYSTEM FOR REQUEST ACCESSING AND SCHEDULINGUS 8,078,786 · 2011 MANAGING BUFFER STORAGE IN A PARALLEL PROCESSING ENVIRONMENTUS 7,853,774 · 2010 WRITEABLE SHIFT REGISTER LOOKUP TABLE IN FPGA WITH SRAM MEMORY CELLS IN LOOKUP TABLE REPROGRAMMED BY WRITING AFTER INITIAL CONFIGURATIONUS 7,463,056 · 2008 ORDERING RULE AND FAIRNESS IMPLEMENTATIONUS 7,412,555 · 2008 METHOD AND APPARATUS OF MEMORY CLEARING WITH MONITORING RAM MEMORY CELLS IN A FIELD PROGRAMMABLE GATED ARRAYUS 6,937,063 · 2005 MULTICONFIGURATION MODULE FOR HARDWARE PLATFORMSUS 6,867,614 · 2005 APPARATUS AND TECHNIQUE FOR MAINTAINING ORDER AMONG REQUESTS ISSUED OVER AN EXTERNAL BUS OF AN INTERMEDIATE NETWORK NODEUS 6,757,768 · 2004 PROGRAMMBLE LOGIC DEVICE CAPABLE OF PRESERVING USER DATA DURING PARTIAL OR COMPLETE RECONFIGURATIONUS 6,507,211 · 2003 METHOD AND APPARATUS FOR DETECTING A BUS DEADLOCK IN AN ELECTRONIC SYSTEMUS 6,292,910 · 2001 METHOD AND APPARATUS FOR PERFORMING BUS TRANSACTIONS ORDERLY AND CONCURRENTLY IN A BUS BRIDGEUS 6,226,704 · 2001 METHOD OF DESIGNING FPGAS FOR DYNAMICALLY RECONFIGURABLE COMPUTINGUS 6,078,736 · 2000

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