THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

Patent №

US 8,910,171

Granted

2014-12-09

Filed 2010

Owner

LSI CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12974477

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

AI hardwareG06F 15/167G06F 9/3851G06F 9/3885G06F 9/4881H04L 47/522

AI classification

AI hardware1.00
Knowledge representation0.09
Vision0.00
Natural language0.00
Machine learning0.00
Planning0.00
Evolutionary computation0.00
Speech0.00

Ownership

LSI CORPORATION

assignment · 255390204

Assignors

MITAL, DEEPAK, CLEE, JAMES, PIROG, JERRY

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC