LOW LATENCY DYNAMIC ROUTE SELECTION

Patent №

US 8,934,347

Granted

2015-01-13

Filed 2010

Owner

TILERA CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12886346

Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.

AI hardwareG06F 9/4825G06F 9/3004G06F 9/4881G06F 9/5022G06F 9/544G06F 12/00G06F 12/02G06F 12/0806+30 more

AI classification

AI hardware0.88
Knowledge representation0.05
Evolutionary computation0.00
Planning0.00
Machine learning0.00
Speech0.00
Natural language0.00
Vision0.00

Ownership

TILERA CORPORATION

assignment · 252070876

Assignors

BRATT, IAN RUDOLF, RAMEY, CARL G., MATTINA, MATTHEW

On an employer assignment, the assignors are typically the inventors.

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