TESSELLATION SHADER INTER-THREAD COORDINATION

Patent №

US 9,024,946

Granted

2015-05-05

Filed 2010

Owner

NVIDIA CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12879976

One embodiment of the present invention sets forth a technique for performing a computer-implemented method for tessellating patches. An input block is received that defines a plurality of input patch attributes for each patch as well as instructions for processing each input patch. A plurality of threads is launched to execute the instructions to generate each vertex of a corresponding output patch based on the input patch. Reads of values written during instruction execution are synchronized so threads can read and further process the values of other threads. An output patch is then assembled from the outputs of each of the threads; and emitting the output patch for further processing.

AI hardwareG06T 15/005G06T 1/20G06T 15/80G09G 5/363G06F 13/1605

AI classification

AI hardware1.00
Natural language0.06
Vision0.04
Planning0.02
Machine learning0.00
Knowledge representation0.00
Evolutionary computation0.00
Speech0.00

Ownership

NVIDIA CORPORATION

assignment · 249760157

Assignors

BROWN, PATRICK R., DODD, CHRISTOPHER T., KILGARD, MARK J.

On an employer assignment, the assignors are typically the inventors.

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