SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME

A semiconductor memory device includes a plurality of memory cells and a control circuit configured to apply a program voltage of an initial level to a control electrode of a selected memory cell and then of an increased level a number of times, each time without decreasing the program voltage applied to the control electrode, prior to executing a program verifying operation on the selected memory cell. In addition, the control circuit may further be configured to apply an erase voltage of an initial level to a control electrode of a selected memory cell and then of an increased level a number of times, each time without decreasing the erase voltage applied to the control electrode, prior to executing an erase verifying operation on the selected memory cell.