IDLE POWER REDUCTION FOR MEMORY SUBSYSTEMS

Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions.Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.