Patent №
US 9,104,515
Granted
2015-08-11
Filed 2012
Owner
FUJITSU LIMITED
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13715707
An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision.
AI classification
Ownership
FUJITSU LIMITED
assignment · 294840512
Assignors
TOMONO, MITSURU, YOSHIDA, HIROAKI, ANIYA, SOSEKI
On an employer assignment, the assignors are typically the inventors.