Low Density Parity Check Decoder With Dynamic Scaling

Patent №

US 9,130,589

Granted

2015-09-08

Filed 2013

Owner

LSI CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13777841

A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

AI hardwareH03M 13/1117G11B 20/1833H03M 13/1111H03M 13/1171H03M 13/6331H03M 13/658G11B 2020/185H03M 13/27

AI classification

AI hardware1.00
Knowledge representation0.38
Natural language0.04
Machine learning0.02
Vision0.00
Evolutionary computation0.00
Planning0.00
Speech0.00

Ownership

LSI CORPORATION

assignment · 298800292

Assignors

LI, SHU, LI, ZONGWANG, YANG, SHAOHUA, WANG, CHUNG-LI, ZHANG, FAN

On an employer assignment, the assignors are typically the inventors.

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