Patent №
US 9,130,589
Granted
2015-09-08
Filed 2013
Owner
LSI CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13777841
A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.
AI classification
Ownership
LSI CORPORATION
assignment · 298800292
Assignors
LI, SHU, LI, ZONGWANG, YANG, SHAOHUA, WANG, CHUNG-LI, ZHANG, FAN
On an employer assignment, the assignors are typically the inventors.