METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS
Patent №
US 9,201,992
Granted
2015-12-01
Filed 2014
Owner
ATRENTA, INC.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14184021
A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.
AI classification
Ownership
ATRENTA, INC.
assignment · 322490191
Assignors
GANGADHARAN, SRIDHAR, CHAKRABARTI, BARSNEYA, GOEL, MANISH, MOVAHED-EZAZI, MOHAMMAD H.
On an employer assignment, the assignors are typically the inventors.