METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS

Patent №

US 9,201,992

Granted

2015-12-01

Filed 2014

Owner

ATRENTA, INC.

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14184021

A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

PlanningG06F 30/3312G06F 2119/12

AI classification

Planning0.72
Knowledge representation0.04
AI hardware0.04
Natural language0.01
Evolutionary computation0.00
Vision0.00
Speech0.00
Machine learning0.00

Ownership

ATRENTA, INC.

assignment · 322490191

Assignors

GANGADHARAN, SRIDHAR, CHAKRABARTI, BARSNEYA, GOEL, MANISH, MOVAHED-EZAZI, MOHAMMAD H.

On an employer assignment, the assignors are typically the inventors.

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