DATA PROCESSOR CHIP WITH FLEXIBLE BUS SYSTEM

Patent №

US 9,256,575

Granted

2016-02-09

Filed 2015

Owner

—

Lab

—

AI components

ml · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

14718516

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Machine learning AI hardwareG06F 13/4027G06F 9/3001G06F 13/4022G06F 15/7825G06F 15/7867G06F 15/80G06F 15/8023G06F 15/8092+2 more

Google Patents

AI classification

AI hardware0.97

Machine learning0.56

Vision0.09

Knowledge representation0.00

Speech0.00

Natural language0.00

Evolutionary computation0.00

Planning0.00

Cites (73)

LOGICAL CELL ARRAY AND BUS SYSTEMUS 9,047,440 · 2015 DATA PROCESSING METHOD AND DEVICEUS 8,156,284 · 2012 MULTI-CORE PROCESSING SYSTEMUS 7,928,763 · 2011 METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATAUS 7,581,076 · 2009 METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURESUS 7,266,725 · 2007 METHOD FOR TRANSLATING PROGRAMS FOR RECONFIGURABLE ARCHITECTURESUS 7,210,129 · 2007 RUN-AHEAD PROGRAM EXECUTION WITH VALUE PREDICTIONUS 7,188,234 · 2007 AUTOMATED PROCESSOR GENERATION SYSTEM FOR DESIGNING A CONFIGURABLE PROCESSOR AND METHOD FOR THE SAMEUS 7,036,106 · 2006 REAL TIME DSP LOAD MANAGEMENT SYSTEMUS 6,925,641 · 2005 ADAPTIVE SCHEDULING OF FUNCTION CALLS IN DYNAMIC RECONFIGURABLE LOGICUS 6,871,341 · 2005 CONTROLLING VLIW INSTRUCTION OPERATIONS SUPPLY TO FUNCTIONAL UNITS USING SWITCHES BASED ON CONDITION HEAD FIELDUS 6,865,662 · 2005 DEPENDENCY CHECKING FOR RECONFIGURABLE LOGICUS 6,799,265 · 2004 METHOD FOR DETERMINING AN OPTIMAL PARTITIONING OF DATA AMONG SEVERAL MEMORIESUS 6,757,892 · 2004 METHOD FOR COMPILING HIGH LEVEL PROGRAMMING LANGUAGESUS 6,708,325 · 2004 SOFTWARE SANITY MONITORUS 6,665,758 · 2003 RECONFIGURABLE PROGRAMMABLE LOGIC DEVICE COMPUTER SYSTEMUS 6,658,564 · 2003 MULTI-SCALE PROGRAMMABLE ARRAYUS 6,633,181 · 2003 INFORMATION PROCESSING APPARATUS PROVIDED WITH AN OPTIMIZED EXECUTABLE INSTRUCTION EXTRACTING UNIT FOR EXTENDING COMPRESSED INSTRUCTIONSUS 6,587,939 · 2003 MULTIPROCESSOR COMPUTER SYSTEM WITH SECTORED CACHE LINE MECHANISM FOR CACHE INTERVENTIONUS 6,571,322 · 2003 DEVICES AND METHODS WITH PROGRAMMABLE LOGIC AND DIGITAL SIGNAL PROCESSING REGIONSUS 6,538,470 · 2003 RECONFIGURABLE SIMD COPROCESSOR ARCHITECTURE FOR SUM OF ABSOLUTE DIFFERENCES AND SYMMETRIC FILTERING(SCALABLEMAC ENGINE FOR IMAGE PROCESSING)US 6,526,430 · 2003 PROCESSOR, PROGRAMMABLE LOGIC, AND BUS ON A SINGLE INTEGRATED CIRCUITUS 6,467,009 · 2002 SCALEABLE SHARED-MEMORY MULTI-PROCESSOR COMPUTER SYSTEM HAVING REPETITIVE CHIP STRUCTURE WITH EFFICIENT BUSING AND COHERENCE CONTROLSUS 6,457,100 · 2002 REAL TIME PROCESSOR CAPABLE OF CONCURRENTLY RUNNING MULTIPLE INDEPENDENT JAVA MACHINESUS 6,374,286 · 2002 SDRAM L3 CACHE USING SPECULATIVE LOADS WITH COMMAND ABORTS TO LOWER LATENCYUS 6,321,296 · 2001

and 48 more

Related research

Data Rearrange Unit for Efficient Data Computation in Embedded SystemsOpenAlex A Hierarchy of Machine Learning Processing Elements with Joint Micro Programmable Computation and IndexingOpenAlex 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning ApplicationsSemantic Scholar 29.4 Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a Large Multicore Processor for Machine Learning ApplicationsSemantic Scholar Multioperation Mode Ferroelectric Channel Devices for Memory and ComputationSemantic Scholar

Full text

Google Patents