HIERARCHICAL POWER MANAGEMENT CIRCUIT, POWER MANAGEMENT METHOD USING THE SAME, AND SYSTEM ON CHIP INCLUDING THE HIERARCHICAL POWER MANAGEMENT CIRCUIT

A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1<i<N) power management circuit from among the N power management circuits manages supply of power to an (i+1)th power domain from among the N power domains in response to a power management request signal output from a first power management circuit from among the N power management circuits.