Maintenance Of Cache And Tags In A Translation Lookaside Buffer

Patent №

US 9,268,694

Granted

2016-02-23

Filed 2013

Owner

CAVIUM, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14038225

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.

AI hardwareG06F 12/0808G06F 12/1036G06F 12/0802G06F 12/0888G06F 12/10G06F 12/1027G06F 12/1045G06F 2212/151+1 more

AI classification

AI hardware0.96
Natural language0.02
Vision0.00
Evolutionary computation0.00
Machine learning0.00
Knowledge representation0.00
Speech0.00
Planning0.00

Ownership

CAVIUM, INC.

assignment · 319830048

Assignors

SNYDER, WILSON P., II, CHIN, BRYAN W., MUKHERJEE, SHUBHENDU S., BERTONE, MICHAEL, KESSLER, RICHARD E.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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