REAL-TIME CODE AND DATA PROTECTION VIA CPU TRANSACTIONAL MEMORY SUPPORT

Patent №

US 9,507,938

Granted

2016-11-29

Filed 2014

Owner

MCAFEE INC.

Lab

AI components

2

planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14581099

A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking includes creating output code, identifying read-only memory regions in the output code and creating a map that is provided to a security monitoring thread. The security monitoring thread executes as a transaction and determines if a transactional conflict occurs to the read-only memory region during parallel execution of a monitored thread in the output code.

PlanningAI hardwareG06F 9/467G06F 12/1475G06F 21/56G06F 2212/1052

AI classification

AI hardware1.00
Planning0.96
Knowledge representation0.02
Natural language0.01
Machine learning0.01
Evolutionary computation0.00
Speech0.00
Vision0.00

Ownership

MCAFEE INC.

assignment · 390100296

Assignors

MUTTIK, IGOR, NAYSHTUT, ALEX, BULYGIN, YURIY, FURTAK, ANDREW A., DEMENTIEV, ROMAN, MUTTIK, IGOR, NAYSHTUT, ALEX, BULYGIN, YURIY, FURTAK, ANDREW A., DEMENTIEV, ROMAN

On an employer assignment, the assignors are typically the inventors.

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