Patent №
US 9,529,590
Granted
2016-12-27
Filed 2014
Owner
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Lab
AI components
2
ml · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14281132
A node processor and method for performing matrix operations includes storing, in memory, non-zero matrix elements of a first sparse matrix, non-zero matrix elements of a second sparse matrix, and matrix elements of a sparse results matrix mapped to the node processor. A matrix communications module exchanges with other node processors, non-zero matrix elements of one or more of the first sparse matrix, second sparse matrix, and sparse results matrix. An arithmetic logic unit generates partial results based on the non-zero matrix elements of the first sparse matrix and on the non-zero matrix elements of the second sparse matrix stored in memory. The arithmetic logic unit further generates a final value for each matrix element of the sparse results matrix mapped to the node processor based on the partial results generated by the arithmetic logic unit and on partial results received from the other node processors.
AI classification
Ownership
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
assignment · 393020777
Assignors
SONG, WILLIAM S.
On an employer assignment, the assignors are typically the inventors.