INTERRUPT SUPPRESSION STRATEGY

The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state.