PARALLEL LOW-DENSITY PARITY CHECK (LDPC) ACCUMULATION

Patent №

US 9,705,532

Granted

2017-07-11

Filed 2014

Owner

ARRIS ENTERPRISES, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14207459

Systems and methods for parallel accumulation of information bits as part of the generation of low-density parity-check codes are provided. Consecutive information bits can be accumulated through vector operations where the parity addresses used for accumulation can be made contiguous through a virtual to private parity address map. The method for accumulating a set of parity bits for an encoding operation may comprise the steps of performing an exclusive or (XOR) between a multi-bit vector containing information bits and a multi-bit vector of parity bits in an encoder, and storing results of the XOR as a set of parity bits. An encoder for accumulating the set of parity bits is also provided.

AI hardwareH03M 13/6561H03M 13/1165H03M 13/611H03M 13/6505H04L 1/0057

AI classification

AI hardware0.74
Knowledge representation0.03
Vision0.01
Evolutionary computation0.00
Planning0.00
Natural language0.00
Machine learning0.00
Speech0.00

Ownership

ARRIS ENTERPRISES, INC.

assignment · 330140094

Assignors

KHARKUNOU, YURY

On an employer assignment, the assignors are typically the inventors.

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