SYSTEMS AND METHODS FOR FLUSHING A CACHE WITH MODIFIED DATA

Patent №

US 9,710,399

Granted

2017-07-18

Filed 2012

Owner

SOFT MACHINES, INC.

Lab

—

AI components

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13561491

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Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

Knowledge representationG06F 12/128G06F 12/0802G06F 12/0808G06F 12/0811G06F 12/126G06F 12/12G06F 2212/283G06F 2212/608+1 more

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Knowledge representation0.68

AI hardware0.21

Planning0.01

Machine learning0.01

Natural language0.00

Evolutionary computation0.00

Vision0.00

Speech0.00

Ownership

SOFT MACHINES, INC.

assignment · 286740806

Assignors

AVUDAIYAPPAN, KARTHIKEYAN, ABDALLAH, MOHAMMAD

On an employer assignment, the assignors are typically the inventors.

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Cites (57)

auto-commit memory synchronizationUS 9,047,178 · 2015 SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFERUS 8,930,674 · 2015 Multi-Class Data Cache PoliciesUS 8,868,838 · 2014 MANAGING CONCURRENT ACCESSES TO A CACHEUS 8,301,847 · 2012 SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGEUS 8,239,656 · 2012 MEMORY CONTROLLER WITH WRITE DATA CACHE AND READ DATA CACHEUS 8,145,844 · 2012 SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGEUS 7,913,058 · 2011 SINGLE INTERCONNECT PROVIDING READ AND WRITE ACCESS TO A MEMORY SHARED BY CONCURRENT THREADSUS 7,680,988 · 2010 EFFICIENT TRACE CACHE MANAGEMENT DURING SELF-MODIFYING CODE PROCESSINGUS 7,546,420 · 2009 SPECULATIVE INSTRUCTION LOAD CONTROLUS 7,406,581 · 2008 SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGEUS 7,380,096 · 2008 VIRTUALIZATION SYSTEM FOR COMPUTERS HAVING MULTIPLE PROTECTION MECHANISMSUS 7,278,030 · 2007 CONSERVATIVE SHADOW CACHE SUPPORT IN A POINT-TO-POINT CONNECTED MULTIPROCESSING NODEUS 7,213,106 · 2007 SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGEUS 7,149,872 · 2006 METHOD AND APPARATUS FOR DYNAMIC BRANCH PREDICTION UTILIZING MULTIPLE STEW ALGORITHMS FOR INDEXING A GLOBAL HISTORYUS 7,143,273 · 2006 TLB MISS FAULT HANDLER AND METHOD FOR ACCESSING MULTIPLE PAGE TABLESUS 7,111,145 · 2006 VIRTUAL TRANSLATION LOOKASIDE BUFFERUS 6,907,600 · 2005 TEMPLATE SET FOR GENERATING A HYPERTEXT FOR DISPLAYING A PROGRAM GUIDE AND SUBSCRIBER TERMINAL WITH EPG FUNCTION USING SUCH SET BROADCAST FROM HEADENDUS 6,681,395 · 2004 PROVIDING GLOBAL TRANSLATIONS WITH ADDRESS SPACE NUMBERSUS 6,604,187 · 2003 MEMORY SYSTEM FOR MULTIPLE DATA TYPESUS 6,557,083 · 2003 PROCESSOR AND METHOD INCLUDING A CACHE HAVING CONFIRMATION BITS FOR IMPROVING ADDRESS PREDICTABLE BRANCH INSTRUCTION TARGET PREDICTIONSUS 6,457,120 · 2002 BRANCH PREDICTION ARCHITECTUREUS 6,332,189 · 2001 METHOD AND APPARATUS FOR TLB MEMORY ORDERINGUS 6,260,131 · 2001 METHOD AND APPARATUS FOR BRANCH INSTRUCTION PROCESSING IN A PROCESSORUS 6,260,138 · 2001 METHOD AND SYSTEM FOR FETCHING NONCONTIGUOUS INSTRUCTIONS IN A SINGLE CLOCK CYCLEUS 6,256,727 · 2001

and 32 more

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