Patent №
US 9,715,428
Granted
2017-07-25
Filed 2014
Owner
SARATOGA SPEED, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14552355
A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.
AI classification
Ownership
SARATOGA SPEED, INC.
assignment · 378260452
Assignors
MORSHED, ABBAS, TSANG, CHUAN-WEN GEORGE, YOUNGWORTH, CHRISTOPHER
On an employer assignment, the assignors are typically the inventors.