Flicker Reduction Circuit and Method for Compressed Video Transmission

Patent №

US 9,723,314

Granted

2017-08-01

Filed 2012

Owner

SMSC HOLDINGS SARL

Lab

AI components

1

vision

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13408431

A system, circuit and method are provided herein for reducing perceived flicker in video images transmitted using compression and bit rate control. According to one embodiment of the method, a parameter used in the video compression scheme is stored. The parameter stored is one that is subject to adjustment during normal operation of the video compression scheme. Compressed video frame data issued by a compression encoder is used to test for a still-picture condition. When a still-picture condition is detected, the value of the parameter used by the video compression scheme is fixed to the stored value for the duration of the still-picture condition. An embodiment of the system includes an encoder, buffer, bit rate controller, and flicker reduction circuit. An embodiment of the flicker reduction circuit includes a still-picture detection circuit operably coupled to a compressed data path beginning at the output of the encoder.

VisionH04N 19/152H04N 19/107H04N 19/124

AI classification

Vision0.97
AI hardware0.01
Natural language0.00
Evolutionary computation0.00
Speech0.00
Machine learning0.00
Planning0.00
Knowledge representation0.00

Ownership

SMSC HOLDINGS SARL

assignment · 277830939

Assignors

SHETTY, SANTOSH, CHAO, SHIH-CHUNG

On an employer assignment, the assignors are typically the inventors.

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