HARDWARE ACCELERATION FOR INLINE CACHES IN DYNAMIC LANGUAGES

Patent №

US 9,740,504

Granted

2017-08-22

Filed 2014

Owner

QUALCOMM INCORPORATED

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14262871

Aspects include apparatuses, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

AI hardwareG06F 9/4491G06F 12/0802

AI classification

AI hardware1.00
Knowledge representation0.00
Evolutionary computation0.00
Natural language0.00
Speech0.00
Machine learning0.00
Planning0.00
Vision0.00

Ownership

QUALCOMM INCORPORATED

assignment · 328800745

Assignors

ROBATMILI, BEHNAM, CASCAVAL, GHEORGHE CALIN, KEDLAYA, MADHUKAR NAGARAJA, SUAREZ GRACIA, DARIO

On an employer assignment, the assignors are typically the inventors.

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