Patent №
US 9,754,061
Granted
2017-09-05
Filed 2016
Owner
UNIVERSITE DE RENNES 1
+1 more
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
15110064
A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.
AI classification
Ownership
UNIVERSITE DE RENNES 1
assignment · 414890758
INRIA
assignment · 414890758
Assignors
SENTIEYS, OLIVIER, PILLEMENT, SÉBASTIEN, HURIAUX, CHRISTOPHE, COURTAY, ANTOINE
On an employer assignment, the assignors are typically the inventors.