Patent №
US 9,768,767
Granted
2017-09-19
Filed 2016
Owner
ARISTAEUS HERMES LLC
+2 more
AI components
2
planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
15336808
A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.
AI classification
Ownership
ARISTAEUS HERMES LLC
assignment · 401800819
EMPIRE TECHNOLOGY DEVELOPMENT LLC
assignment · 401800834
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
assignment · 543780836
Assignors
POTKONJAK, MIODRAG, ARISTAEUS HERMES LLC
On an employer assignment, the assignors are typically the inventors.