ALIGNMENT DETECTION IN A MULTI-LANE NETWORK INTERFACE

In an example implementation, an alignment detection circuit includes a buffer, a candidate selection circuit, and a correlator circuit. The buffer is configured to receive a data stream from a data lane, the data stream including alignment markers delineating data frames, each of the alignment markers having a predefined bit pattern. The candidate selection circuit is configured to identify candidate data blocks in successive data blocks of the data stream provided by the buffer, each of the candidate blocks having a measure of symmetry satisfying a threshold metric indicative of the predefined bit pattern. The correlator circuit is configured to search for at least one of the alignment markers in each of the candidate blocks and adjust alignment of the data stream in the buffer in response to locating the at least one alignment marker.