Reducing Write-Backs to Memory by Controlling the Age Of Cache Lines In Lower Level Cache

Patent №

US 9,952,973

Granted

2018-04-24

Filed 2015

Owner

HGST NETHERLANDS B.V.

Lab

AI components

2

planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14927410

A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

PlanningAI hardwareG06F 12/0833G06F 12/0804G06F 12/0806G06F 12/122G06F 12/123G06F 12/128G06F 12/12G06F 2212/1016+2 more

AI classification

AI hardware0.99
Planning0.76
Machine learning0.03
Knowledge representation0.03
Natural language0.02
Evolutionary computation0.00
Speech0.00
Vision0.00

Ownership

HGST NETHERLANDS B.V.

assignment · 369360396

Assignors

KAMRUZZAMAN, MD

On an employer assignment, the assignors are typically the inventors.

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