Patent №
US 9,952,987
Granted
2018-04-24
Filed 2014
Owner
INTEL CORPORATION
Lab
—
AI components
2
planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14553430
An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.
AI classification
Ownership
INTEL CORPORATION
assignment · 354430183
Assignors
GUDDETI, JAYAKRISHNA, CHANG, LUKE, SANKARAN, RAJESH M., THALIYIL, JUNAID F.
On an employer assignment, the assignors are typically the inventors.