ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES
Patent №
US 9,990,455
Granted
2018-06-05
Filed 2017
Owner
TACTOTEK OY
Lab
—
AI components
2
planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
15840549
An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.
AI classification
Ownership
TACTOTEK OY
assignment · 443930446
Assignors
SINIVAARA, HASSE, HEIKKILA, TUOMAS, KERANEN, ANTTI
On an employer assignment, the assignors are typically the inventors.