We present a novel approach for digital hardware simulation based on many-valued (fuzzy) logic (MVL). Binary designs can be automatically transformed into MVL designs, and simulations performed in the more informative MVL setting may reveal details which are either invisible or hard to detect through binary simulations. Two circuits which are supposed to be binary equivalent may behave differently under MVL simulations, and analyzing these differences may lead to the discovery of a genuine binary nonequivalence, or in some cases, to a qualitative gap between the designs. By performing an MVL simulation, a combinational design becomes a union of trajectories, where each trajectory starts at some input variable and all the nodes along the trajectory are of the same degree of veracity or falsehood. With sequential synchronous designs one can incorporate temporal data into the simulation, so that the state of the design at a given time reports besides the degree of truth of each variable also the place and date of birth of its value. Applications include equivalence verification, initialization, assertions generation and verification, stuck-at-values, partial control on the flow of data by prioritizing, block-oriented simulations. Some procedures and general directions towards achieving these goals are presented.