MODELING AND VERIFYING THE INTENDED FLOW OF LOGICAL SIFNALS IN A HARDWARE DESIGN

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a method is provided for explicitly associating state information with variables of a language description of a hardware design. Information regarding the intended flow of logical signals among the variables, which represent interconnects in the hardware design through with the logical signals pass, is received. Then, the intended flow of logical signals is modeled by associating state information with the variables in accordance with the intended flow of logical signals. Advantageously, in this manner, the integrity of the data flow can be verified by confirming checks that are expressed as a function of the states associated with the variables.