Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. Recently, reinforcement learning (RL) has emerged as a promising technique for improving placement quality, especially macro placement. However, current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results. A key issue lies in the problem formulation, i.e., using RL to place from scratch, which results in limits useful information and inaccurate rewards during the training process. In this work, we propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts, thereby receiving sufficient information for the policy to act and obtain relatively dense and precise rewards. Additionally, we introduce the concept of regularity during training, which is considered an important metric in the chip design industry but is often overlooked in current RL placement methods. We evaluate our approach on the ISPD 2005 and ICCAD 2015 benchmark, comparing the global half-perimeter wirelength and regularity of our proposed method against several competitive approaches. Besides, we test the PPA performance using commercial software, showing that RL as a regulator can achieve significant PPA improvements. Our RL regulator can fine-tune placements from any method and enhance their quality. Our work opens up new possibilities for the application of RL in placement, providing a more effective and efficient approach to optimizing chip design. Our code is available at \url{https://github.com/lamda-bbo/macro-regulator}.

Paper

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Peer review

Reviewer XyiM6/10 · confidence 3/52024-07-11

Summary

The paper proposes MaskRegulate, a method that utilizes reinforcement learning in the refinement stage for time-efficient training and accurate reward generation. Additionally, the authors introduce a regularity metric that can be used alongside HPWL in chip placement. To validate their proposed method, the authors evaluated the PPA performance, a real-world metric and compared with competitive baselines.

Strengths

- This paper highlights that a major challenge in applying RL to chip placement is the problem formulation. - The proposed MaskRegulate introduces the concept of regularity, which has been overlooked in previous works, and achieves state-of-the-art performance. - The authors validated their proposed method by evaluating it on the ICCAD 2015 benchmark and comparing it with competitive baselines. Furthermore, they assessed the real-world metric, PPA, using a commercial EDA tool to ensure the method's practicality in industry applications. - The visualization results in Figure 6 are impressive and effectively demonstrate the effectiveness of the proposed method. If possible, I recommend including some of these visualizations from Figure 6 in the main paper.

Weaknesses

The overall presentation of the paper requires improvement, particularly in the clarity of labels and explanations for figures. Figure 3(a) is especially problematic, as the labels 'adjusting' and 'adjusted' are ambiguous and do not clearly indicate which blocks they refer to. To avoid potential misinterpretation, it is crucial to enhance both the figure and its accompanying explanation. Addressing these issues will significantly improve the paper's clarity and prevent possible misunderstandings.

Questions

1. How does the model determine adjusted and unadjusted macros? Are the macros adjusted sequentially? If so, how is the order of sequence determined? 2. What happens if the model encounters a situation where no feasible space is available? Does it re-adjust previously adjusted macros? 3. In section 4.4, you mentioned using alpha=0.7 for experiments. Do these experiments refer to the results in Table 1 and Table 2? If so, please explicitly state this, as Figure 4 suggests that alpha is a very important hyperparameter.

Rating

6

Confidence

3

Soundness

4

Presentation

2

Contribution

4

Limitations

- Apart from some presentation-related issues, I do not observe any significant limitations in this paper. - To further strengthen the quality of the work, the authors might consider including training convergence graphs for ChipFormer and MaskRegulate.

Reviewer fJAy5/10 · confidence 5/52024-07-12

Summary

This paper utilizes an online RL algorithm to adjust the existing placement layouts, instead of placing the blocks on the scratch. Additionally, the paper introduces one heuristic concept regularity, which better regularity results in higher PPA performance. Besides, this paper tests the PPA performance using commercial software, showing their methods can achieve significant PPA improvements. Experiments show the proposed method improves PPA performance and proxy in the ICCAD 2015 benchmark compared to the state-of-the-art placement works.

Strengths

1. The paper introduces the new metric regularity, which is the heuristic knowledge by experienced engineers. Compared to the proxy metrics commonly used in previous work, it is more reflected in the PPA performance which is a more important metric considered by the industry. 2. The paper uses the commercial EDA tool to evaluate the efficiency of their methods. The results of the EDA tool analysis are convincing, and the performance is superior to the previous methods.

Weaknesses

Several technical details need to be explained. 1. The most concerning part is the new MDP. The action space is not well described. Compared to MaskPlace, MaskRegulate places the blocks based on the full placement results. So, if the current placing block is placed in an already occupied position, would the occupied block be switched by the current block, or the occupied block be plugged off the board? Compared to placing the blocks one by one, the termination function is clear that the episode would end once all blocks are placed. In this paper, the termination function is not clear since each step is the full placement with all blocks on the board. What is the termination function in this MDP? 2. WireMask feature map calculation is also ambiguous in this paper. Since the WireMask feature map is proposed in the MDP that places blocks one by one, it describes the amounts of gains in HPWL when placing the current block on each grid. But, in your MDP, the block seemed to be switched (related to the first question). How do you calculate the WireMask in your case? 3. In the generalization part, for the unseen chips, is the model training part frozen to do forward inferences only?

Questions

Please see the pros and cons part.

Rating

5

Confidence

5

Soundness

2

Presentation

1

Contribution

3

Limitations

The regularity is one heuristic knowledge summarized by experienced engineers. As the introduction in section 3.2 “Why does regularity matters?”, the engineer prefers to place macros toward the peripheral regions of the chip. Is it possible that there exists some other unknown heuristics, like rectangular shape, or triangle shape that also impact a good performance? It may be the open question that applying the existing human heuristic knowledge constraints the agent explores the whole state-action design space.

Reviewer KS3m7/10 · confidence 4/52024-07-13

Summary

This paper proposes a novel approach called MaskRegulate for the refinement stage of macro placement, using reinforcement learning (RL) methods. Specifically, it trains an RL policy to adjust the existing placement layouts, from which the policy can receive sufficient information, instead of placing from scratch. Regularity is also considered during the learning process, helping to enhance the placement quality. Experiments demonstrate that it outperforms previous competitive approaches, achieving significant half-perimeter wirelength (HPWL), power, performance, and area (PPA) improvements.

Strengths

1. This paper first explores RL method as a regulator instead of a placer, providing a more effective and efficient approach to optimizing chip design. 2. Regular mask is employed to guide the learning process, which greatly improves the regularity of the chip layouts. 3. PPA metrics are considered for a comprehensive analysis, showing the practical applicability and effectiveness of MaskRegulate. 4. The experiments are sufficient and solid, showing the great refinement and generalization ability of MaskRegulate.

Weaknesses

1. Regularity is also proposed in other works such as [1]. This paper does not discuss how it differs from them. 2. The paper lacks some discussion on the necessity of using RL other than other methods as the regulator. [1] A. Vidal-Obiols, J. Cortadella, J. Petit, M. Galceran-Oms, and F. Martorell. Rtl-aware dataflow-driven macro placement. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE), 2019.

Questions

1. Can the regular mask be used in [2] WireMask-BBO? 2. Why does GP HPWL improve since only MP HPWL is considered in the learning process? [2] Y. Shi, K. Xue, L. Song, and C. Qian. Macro placement by wire-mask-guided black-box optimization. In Advances in Neural Information Processing Systems 36, New Orleans, LA, 2023.

Rating

7

Confidence

4

Soundness

3

Presentation

3

Contribution

3

Limitations

Yes

Reviewer NxAR7/10 · confidence 5/52024-07-17

Summary

This paper introduces a Macro Regulator that uses reinforcement learning (RL) to optimize existing macro placements. It reconsiders the application of RL in macro placement and incorporates a regularity metric into the reward function. The paper presents a comprehensive set of comparative experiments to ultimately demonstrate the superiority of the Macro Regulator. Ablation studies also confirm the effectiveness of each component in the proposed approach. The contributions of the paper are specified as follows: Firstly, Macro Regulator shifts the focus of RL from placing macros from scratch to refining existing macro placements. This approach enables the RL policy to utilize more state information and achieve more accurate reward signals, enhancing learning efficiency and final PPA quality. Secondly, the paper introduces the concept of regularity into the RL framework, a crucial metric often overlooked in chip design. By incorporating regularity as part of the input information and reward signal, Macro Regulator ensures consistency in manufacturing and performance. Thirdly, the proposed method is evaluated on the ICCAD 2015 benchmark, demonstrating superior performance in terms of global placement half-perimeter wire length (HPWL) and regularity compared to various competing methods. Additionally, PPA metrics are tested using the commercial EDA tool Cadence Innovus, showing significant improvements.

Strengths

In summary, this paper makes a substantial contribution to the field of chip design through its novel problem formulation and high-quality experimental methodology. The originality of integrating regularity into the RL framework and the thoroughness of the experimental validation are particularly noteworthy. This work advances the state of the art in macro placement. 1. Originality - Novel Problem Definition: The paper introduces a new problem formulation by shifting the focus from using RL to place from scratch to refining existing macro placements. This innovative approach allows for more efficient use of state information and more precise reward signals. - Integration of Regularity: The inclusion of regularity as a key metric in the RL framework is a novel contribution. Regularity is crucial for ensuring manufacturing consistency and performance but is often overlooked in existing methods. 2. Quality - Robust Methodology: The paper employs a comprehensive experimental methodology, utilizing the ICCAD 2015 benchmark and commercial EDA tools (Cadence Innovus) for validation. The experiments are well-designed and include comparisons with multiple existing methods. - Detailed Analysis: The paper includes a comprehensive analysis of the proposed method, along with ablation studies that validate the effectiveness of different components. The detailed evaluation and the provided code help to enhance the credibility of the results. 3. Significance - Impact on Chip Design: The proposed Macro Regulator addresses significant limitations of existing RL methods in macro placement, such as training time, reward sparsity, and generalization capability. By improving placement quality and PPA metrics, this work has the potential to significantly impact the efficiency and effectiveness of chip design processes.

Weaknesses

While the paper presents a significant advancement in the field of macro placement using reinforcement learning, there are areas for improvement. Expanding the benchmark scope, including real-world case studies, demonstrating generalization capabilities, and providing more detailed algorithmic descriptions would enhance the overall impact and robustness of the work. Addressing these weaknesses would make the paper's contributions even more compelling and practical for real-world applications. 1. Limited Benchmark Scope - Additional Datasets Needed: While the paper utilizes the ICCAD 2015 benchmark and Cadence Innovus for validation, the scope of the benchmarks is somewhat limited. Including additional datasets or real-world applications could strengthen the evaluation and demonstrate the generalizability of the proposed method. For example, benchmarks from other well-known contests or industrial examples with different characteristics could provide a more comprehensive assessment. 2. Generalization to Different Chip Designs - Generalization Capability: While the paper mentions the generalization capabilities of Macro Regulator, more detailed experiments and analysis on different types of chip designs (e.g., various sizes, complexities, and design constraints) would strengthen the claims. Demonstrating the method's adaptability to a broader range of scenarios would enhance its perceived robustness and applicability. 3. Clarity of Method Description - Detailed Algorithmic Steps: While the paper is generally clear, some parts of the methodology could benefit from more detailed descriptions. For example, providing pseudo-code or more granular steps of the Macro Regulator algorithm would help readers better understand the implementation details and reproduce the results. Additionally, regularity is an important metric, but the paper provides limited explanation of this metric. It would be beneficial to supplement more information about its definition and calculation. Furthermore, a more detailed explanation of essential factors such as the states and actions in reinforcement learning would enhance the paper.

Questions

In the abstract, the author states, "Our RL regulator can fine-tune placements from any method and enhance their quality." However, in the experimental section, it is mentioned, "For each chip, MaskRegulate uses DREAMPlace to obtain an initial macro placement result to be adjusted, which takes within a few minutes and has relatively low quality." There are two issues with this: 1. The claim of "from any method" is not entirely supported as DREAMPlace is essentially an analytical method, thus the experiments can only prove the ability to improve macro placement solutions from analytical methods, not from any other method. 2. The assertion of "relatively low quality" raises the question of whether the MaskRegulate method relies heavily on the quality of initial macro placement result. It would be worthwhile to explore the effect of optimizing from different quality macro placement solutions (such as higher but not the best macro placement result), rather than starting from relatively low-quality ones. In summary, can the MaskRegulate method improve the quality of "any method" and "any quality of initial macro placement solution"?

Rating

7

Confidence

5

Soundness

3

Presentation

2

Contribution

3

Limitations

Yes.

Reviewer ChiY5/10 · confidence 3/52024-07-22

Summary

This paper presents an application of the RL algorithm in chip design optimization. They formulate the chip design process as an MDP process to make decisions based on the current state of the chip macro arrangement so that they can apply PPO to optimize the policies. Compared with starting from scratch, they focus on the fine-tuning stage of the macros for denser reward signals. Their experiments in a public benchmark, the ICCAD 2015 benchmark show a great improvement in the chip design metrics.

Strengths

According to the related work section, although there have been RL methods in this benchmark, this method improves previous methods by starting from macro placements instead of starting from scratch, which is a heuristic way of optimizing and simplifying the problem. This heuristic should be novel when combined with this class of methods. The paper is technically solid in the problem formulation, experiments are sufficient with baselines, and reasonable ablation studies, and the results look good. I like the visualization part of the paper.

Weaknesses

Compared with MaskPlace [1], the contributions of this paper lie in the expertise or experiences in the expert chip design area instead of the machine learning area, as MaskPlace has already used PPO. One thing I am concerned about is that NeurIPS may not be a good venue to discuss this contribution. [1] Lai, Y., Mu, Y., & Luo, P. (2022). Maskplace: Fast chip placement via reinforced visual representation learning. Advances in Neural Information Processing Systems, 35, 24019-24030.

Questions

[1] When you discretize the map, it becomes a combinatorial problem. Did you compare the sample complexity of using RL vs using some combinatorial solver? [2] PPO can handle continuous action space, is there a possibility of improvement using continuous action space? [3] What will be the future directions for this work or is this problem solved by RL?

Rating

5

Confidence

3

Soundness

3

Presentation

3

Contribution

2

Limitations

The authors have discussed the limitations of this work.

Reviewer ChiY2024-08-11

Thank authors for answering my questions, I have adjusted my ratings. Follow-up Q2: I guess your RL method benefits from the reduction in the state/action space, and similarly, combinatorial methods can also benefit from this, was there any baseline run under the same action space or problem setting?

Authorsrebuttal2024-08-12

Thank you for your feedback. We are pleased to hear that your concerns have been addressed and the score has been increased. Regarding the follow-up Q2, we agree that our proposed formulation of RL can also be used for combinatorial methods. To the best of our knowledge, no existing work has used combinatorial optimization under this setting. One may use some suitable combinatorial methods under our proposed RL regulator formulation and the reduction of search space to investigate if they can be improved. We will leave this for future work. Thank you for your insightful suggestions.

Program Chairsdecision2024-09-25

Decision

Accept (poster)

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