As digital designs grow in size and complexity, design verification and debugging failures become increasingly more challenging. Verification today takes up to 70% of all design development cycles. Half of this time is spent on debug. Thus, automating any stage of the debug process would have significant effect on reducing the overall design time. In this paper, we present a tool that uses Machine Learning techniques to analyze and leverage data from failing simulations from regressions to detect which failures are related to actual bugs in the Register Transfer Level (RTL). Debuggers' time can be effectively utilized by prioritizing RTL-defects to be debugged first, which also helps in resolving these defects faster which means better RTL quality. The tool was tested using regression data from an x86 processor verification. A 90% capture rate was achieved for single-defect signatures, as well as a 95% capture rate for multi-defect signatures with reasonable debug overhead.
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Expediting Design Bug Discovery in Regressions of x86 Processors Using Machine Learning
Semantic Scholar · Computer Science · 2019
Abstract
As digital designs grow in size and complexity, design verification and debugging failures become increasingly more challenging. Verification today takes up to 70% of all design development cycles. Half of this time is spent on debug. Thus, automating any stage of the debug process would have significant effect on reducing the overall design time. In this paper, we present a tool that uses Machine Learning techniques to analyze and leverage data from failing simulations from regressions to detect which failures are related to actual bugs in the Register Transfer Level (RTL). Debuggers' time can be effectively utilized by prioritizing RTL-defects to be debugged first, which also helps in resolving these defects faster which means better RTL quality. The tool was tested using regression data from an x86 processor verification. A 90% capture rate was achieved for single-defect signatures, as well as a 95% capture rate for multi-defect signatures with reasonable debug overhead.