HARDWARE-SOFTWARE DEBUGGER USING SIMULATION SPEED ENHANCING TECHNIQUES INCLUDING SKIPPING UNNECESSARY BUS CYCLES, AVOIDING INSTRUCTION FETCH SIMULATION, ELIMINATING THE NEED FOR EXPLICIT CLOCK PULSE GENERATION AND CACHING RESULTS OF INSTRUCTION DECODING

The speed of a hardware-software debugger is markedly increased through the use of high speed simulators which ignore all systems operations except those where design errors are expected to manifest themselves, by skipping CPU bus cycles of no interest for the simulation, by not explicitly simulating periodic clock signals and generating only schedules of clock signals, and by caching instructions when alien computers are used in the simulation process to eliminate decoding of the instructions of the target computer.