FPGA Accelerator for Real-Time Emulation of Power Electronic Systems Using Multiport Decomposition
Development of accurate Real-Time systems with power electronic converters is a challenging task due to its high switching frequency and the time varying circuit topology. This paper explains the strategies to implement power electronic circuit models in real time, by exploiting the parallel and distributed computing nature of FPGA, with three-phase-three-level diode-clamped inverter as a case study. A generic multiport decomposition technique is applied to improve parallelism and to reduce the size of the matrix for the computation. Also, by developing a PySpice based utility, which pre-computes all the system matrices from the given netlist, implementation is made more adaptable to different partitions and circuit variations. Target circuit is implemented in C/C++ language, converted to VHDL and implemented on ZedBoard (XC7Z020) using Xilinx Vivado tools. With this generalized approach, a latency of less than $5\mu\mathrm{s}$ is achieved with reasonable utilization of resources, on FPGA. Real-Time performance of the implemented inverter model with Sine-Pulse-Width-Modulation technique is verified by connecting in loop with the induction motor model for its speed control. A latency of $6.65\mu\mathrm{s}$ is achieved within each simulation time step for the closed loop control of induction motor which is sufficient for the wide range of variable frequency drive applications.
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FPGA Accelerator for Real-Time Emulation of Power Electronic Systems Using Multiport Decomposition
Semantic Scholar · Computer Science · 2019
Abstract
Development of accurate Real-Time systems with power electronic converters is a challenging task due to its high switching frequency and the time varying circuit topology. This paper explains the strategies to implement power electronic circuit models in real time, by exploiting the parallel and distributed computing nature of FPGA, with three-phase-three-level diode-clamped inverter as a case study. A generic multiport decomposition technique is applied to improve parallelism and to reduce the size of the matrix for the computation. Also, by developing a PySpice based utility, which pre-computes all the system matrices from the given netlist, implementation is made more adaptable to different partitions and circuit variations. Target circuit is implemented in C/C++ language, converted to VHDL and implemented on ZedBoard (XC7Z020) using Xilinx Vivado tools. With this generalized approach, a latency of less than $5\mu\mathrm{s}$ is achieved with reasonable utilization of resources, on FPGA. Real-Time performance of the implemented inverter model with Sine-Pulse-Width-Modulation technique is verified by connecting in loop with the induction motor model for its speed control. A latency of $6.65\mu\mathrm{s}$ is achieved within each simulation time step for the closed loop control of induction motor which is sufficient for the wide range of variable frequency drive applications.