SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED SIMULATION ACCELERATION

The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.