Design and optimization of Issue queue in Out-of-Order superscalar microprocessor

Abstract

Issue queue is not only the control component of out-of-order superscalar processor, but also the key power consumption component of the processor, which plays a decisive role in the performance of the whole processor. This paper design a dual-port issue for superscalar processors, and analyses the effect of different issue queue on performance. The queue can estimate the issue time of instructions according to the correlation between instructions, and allocate instructions to different queues. The effects of two different issue strategies on performance are compared. The strategy of input tag execution pipeline can obtain high IPC performance, up to 10.68%. At the same time, the impact of the number of different issue queue items on the performance of the same issue strategy is compared. The floating-point issue queue has little impact on the performance of SPEC2006 integer test, and increasing the number of floating-point issue queue entries can effectively improve the performance of floating-point testing, up to 30%. The number of LSU and branch issue queues only have a slight impact on individual program performance, and increasing the number of issue queue entries may not necessarily achieve effective performance gains.