To address data storage demands in large-scale ad hoc network simulations, this paper designs and implements a hardware buffer management system based on a heterogeneous memory architecture. The system utilizes Block Random Access Memory (BRAM) within the Field Programmable Gate Array (FPGA) as first-level memory, allocating independent local storage partitions for each of the 128 network nodes to enable rapid data access and isolated management. Concurrently, off- chip Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is employed to construct a high-capacity shared memory pool, which serves as a second-level memory to support the storage of large-scale data. Simulation results demonstrate that the design successfully achieves effective storage capacity expansion, providing a reliable and feasible solution for large-scale ad hoc network simulations on resource-constrained FPGA platforms.
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Design of FPGA Memory Architecture for Large-Scale Ad Hoc Network Simulation
Semantic Scholar · Computer Science · 2026
Abstract
To address data storage demands in large-scale ad hoc network simulations, this paper designs and implements a hardware buffer management system based on a heterogeneous memory architecture. The system utilizes Block Random Access Memory (BRAM) within the Field Programmable Gate Array (FPGA) as first-level memory, allocating independent local storage partitions for each of the 128 network nodes to enable rapid data access and isolated management. Concurrently, off- chip Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is employed to construct a high-capacity shared memory pool, which serves as a second-level memory to support the storage of large-scale data. Simulation results demonstrate that the design successfully achieves effective storage capacity expansion, providing a reliable and feasible solution for large-scale ad hoc network simulations on resource-constrained FPGA platforms.