The escalating complexity of system-on-chip (SoC) designs has rendered traditional floor planning a critical physical design stage that is increasingly manual, timeconsuming, and expertise dependent. Although automated tools exist, they often converge to suboptimal solutions and struggle with complex multimodal constraints. This study introduces ChipGPT, a novel framework that leverages the advanced reasoning and sequence modeling capabilities of Large Language Models (LLMs) to automate and optimize SoC floor planning. ChipGPT encodes the netlist, macroproperties, and design constraints into a structured textual prompt. An LLM agent, acting as an intelligent optimizer, interprets the prompt and proposes iterative floorplan refinements. These proposals are evaluated by a cost engine that calculates the wirelength, area, and congestion, with the results fed back to guide subsequent reasoning. On standard benchmarks, ChipGPT demonstrates a $\mathbf{1 5}-\mathbf{3 0 \%}$ reduction in total wirelength compared to conventional simulated-annealing and commercial auto-placer baselines. It generates highquality, human-competitive floor plans in a fraction of the time. This study establishes a new paradigm by demonstrating LLMs' potential of LLMs as intelligent agents for complex, constraint-driven optimization in electronic design automation.
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ChipGPT: Leveraging Large Language Models for Automated and Optimized Soc Floorplanning
Semantic Scholar · 2026
Abstract
The escalating complexity of system-on-chip (SoC) designs has rendered traditional floor planning a critical physical design stage that is increasingly manual, timeconsuming, and expertise dependent. Although automated tools exist, they often converge to suboptimal solutions and struggle with complex multimodal constraints. This study introduces ChipGPT, a novel framework that leverages the advanced reasoning and sequence modeling capabilities of Large Language Models (LLMs) to automate and optimize SoC floor planning. ChipGPT encodes the netlist, macroproperties, and design constraints into a structured textual prompt. An LLM agent, acting as an intelligent optimizer, interprets the prompt and proposes iterative floorplan refinements. These proposals are evaluated by a cost engine that calculates the wirelength, area, and congestion, with the results fed back to guide subsequent reasoning. On standard benchmarks, ChipGPT demonstrates a $\mathbf{1 5}-\mathbf{3 0 %}$ reduction in total wirelength compared to conventional simulated-annealing and commercial auto-placer baselines. It generates highquality, human-competitive floor plans in a fraction of the time. This study establishes a new paradigm by demonstrating LLMs' potential of LLMs as intelligent agents for complex, constraint-driven optimization in electronic design automation.