Intelligent Reinforcement Learning-Based Floor Planning Framework for Multi-Objective Optimization in VLSI Physical Design

Abstract

The increasing complexity of modern Very LargeScale Integration (VLSI) systems has significantly elevated the importance of efficient chip floor planning during the physical design stage. Traditional floor planning approaches often struggle to meet stringent requirements related to area utilization, wirelength minimization, power efficiency, thermal management, and timing constraints, particularly in advanced technology nodes. Recent advancements in Artificial Intelligence (AI) and Machine Learning (ML) have introduced new opportunities for automating and optimizing chip floor planning processes. AI-driven optimization techniques can analyze large design spaces, learn placement patterns, and generate efficient floorplans within significantly reduced computation times. This paper presents a comprehensive study of AI-based floor planning methodologies and proposes an Intelligent Reinforcement Learning Floor planning Framework (IRLFF) for VLSI systems. The proposed framework combines deep reinforcement learning, graph neural networks, and multi-objective optimization techniques to improve placement quality while reducing design turnaround time. Experimental analysis demonstrates significant improvements in area utilization, wirelength reduction, congestion control, and power efficiency compared with conventional floor planning techniques. The results indicate that AI-driven floor planning represents a promising solution for future semiconductor design automation challenges.