PROCESSOR AND METHOD

A processor includes an arithmetic processing circuit, a cache memory including a plurality of ways, a usage information register storing usage information indicating whether to use each of the plurality of ways, a purge control circuit performing purge processing on a basis of rewriting of the usage information within the usage information register according to an instruction executed by the arithmetic processing circuit, the purge processing including processing of deleting, from the cache memory, target data retained in a target way to be stopped and processing of writing back part of the target data, the part of the target data being data rewritten in the cache memory, to a main memory at a lower level than the cache memory, and an access control circuit controlling accessing the cache memory on a basis of a memory access request received from the arithmetic processing circuit and status of the purge processing.