IDENTIFYING ROOT CAUSE OF LAYOUT VERSUS SCHEMATIC ERRORS

A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.