Patent №
US 10,692,571
Granted
2020-06-23
Filed 2019
Owner
JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD.
+1 more
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
16362719
A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read/write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read/write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.
AI classification
Ownership
JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD.
assignment · 486930607
ALTO MEMORY TECHNOLOGY CORPORATION
assignment · 486930607
Assignors
WU, JUI-JEN, JIEN, FAN-YI, HUANG, SHENG-TSAI, ZHENG, JUNHUA
On an employer assignment, the assignors are typically the inventors.