VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR ARCHITECTURE

A vertical transport field-effect transistor architecture is fabricated using a fin-last fabrication technique that enables pre-patterning of sacrificial gate layers and/or sacrificial source/drain layers with substantially flat topography prior to fin formation. Fins are epitaxially grown in trenches extending vertically through the device layers. Discrete regions of the sacrificial layers are later removed and replaced with appropriate source/drain and/or gate materials. Dielectric spacer elements are used to constrain feature dimensions of the replacement materials.