MACHINE LEARNING-BASED CLASSIFICATION IN PARASITIC EXTRACTION AUTOMATION FOR CIRCUIT DESIGN AND VERIFICATION

This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit. The computing system also can implement a machine-learning classifier that, when trained with a training data set, can classify the physical design layout based on physical or electrical characteristics associated with the physical design layout, and can utilize the classification to select a set of scaling coefficients. The computing system can apply the selected set of the scaling coefficients to adjust coupling capacitances in the parasitic model and generate a parasitic netlist for the physical design layout. The computing system can generate the training data set by determining sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.