MAINTENANCE SCHEDULING FOR SEMICONDUCTOR MANUFACTURING EQUIPMENT

Patent №

US 11,295,993

Granted

2022-04-05

Filed 2020

Owner

PDF SOLUTIONS, INC.

Lab

—

AI components

ml · kr · planning · evo · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

17002250

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A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

Machine learning Knowledge representation Planning Evolutionary computation AI hardwareH01L 22/20H10P 74/20G01R 31/2601G01R 31/2831G06N 3/09G06N 3/091G06N 20/00G06N 20/20+6 more

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AI classification

Planning1.00

AI hardware1.00

Machine learning1.00

Knowledge representation0.98

Evolutionary computation0.60

Natural language0.03

Speech0.00

Vision0.00

Ownership

PDF SOLUTIONS, INC.

assignment · 578240939

Assignors

CHEONG, LIN LEE, DAVID, JEFFREY, HONDA, TOMONORI

On an employer assignment, the assignors are typically the inventors.

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Cites (13)

STATISTICAL OVERLAY ERROR PREDICTION FOR FEED FORWARD AND FEEDBACK CORRECTION OF OVERLAY ERRORS, ROOT CAUSE ANALYSIS AND PROCESS CONTROLUS 9,087,176 · 2015 Novel Design of Tool Function to Improve Fab Process in Semiconductor ManufacturingUS 9,002,498 · 2015 DIFFRACTION BASED OVERLAY METROLOGY TOOL AND METHODUS 8,339,595 · 2012 HIERARCHICAL AND INCREMENTAL MULTIVARIATE ANALYSIS FOR PROCESS CONTROLUS 8,233,494 · 2012 APPARATUS AND METHODS FOR PREDICTING A SEMICONDUCTOR PARAMETER ACROSS AN AREA OF A WAFERUS 7,873,585 · 2011 INITIATING TEST RUNS BASED ON FAULT DETECTION RESULTSUS 7,581,140 · 2009 METHOD AND SYSTEM FOR ADVANCED PROCESS CONTROL INCLUDING TOOL DEPENDENT MACHINE CONSTANTSUS 7,403,832 · 2008 LITHOGRAPHY METHOD AND SYSTEM WITH CORRECTION OF OVERLAY OFFSET ERRORS CAUSED BY WAFER PROCESSINGUS 7,184,853 · 2007 YIELD PATROLLING SYSTEMUS 7,117,057 · 2006 COMPUTER-IMPLEMENTED METHOD AND CARRIER MEDIUM CONFIGURED TO GENERATE A SET OF PROCESS PARAMETERS FOR A LITHOGRAPHY PROCESSUS 6,968,253 · 2005 SYSTEM AND SOFTWARE FOR DATA DISTRIBUTION IN SEMICONDUCTOR MANUFACTURING AND METHOD THEREOFUS 6,772,034 · 2004 METHOD AND APPARATUS FOR CORRELATING ERROR MODEL WITH DEFECT DATAUS 6,610,550 · 2003 SYSTEM AND METHOD OF IDENTIFYING THE NUMBER OF CHIP FAILURES ON A WAFER ATTRIBUTED TO CLUSTER FAILURESUS 5,793,650 · 1998

Cited by (2)

METHOD FOR PREDICTING OCCURRENCE OF TOOL PROCESSING EVENT AND VIRTUAL METROLOGY APPLICATION AND COMPUTER PROGRAM PRODUCT THEREOFUS 11,829,124 · 2023 Patent US 11,670,480US 11,670,480

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