SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT RESISTANCE AND VIA CONNECTIVITY

A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.